Concordant memory design using statistical integration for the billions-transistor era

Author

Akiyama, Satoru ; Sekiguchi, Tomonori ; Kajigaya, Kazuhiko ; Hanzawa, Satoru ; Takemura, Riichiro ; Kawahara, Takayuki

Author_Institution

Hitachi Ltd., Kokubunji, Japan

fYear

2005

Firstpage

466

Abstract

An embedded DRAM macro in a logic compatible 90nm CMOS process is designed with low-noise core architecture and high-accuracy post-fabrication tuning. With a 5fF/cell capacitance, a 61% improvement of sensing accuracy enables 322MHz random-cycle operation and reduces data retention power to 60 μW.

Keywords

CMOS logic circuits; CMOS memory circuits; DRAM chips; embedded systems; statistical analysis; 322 MHz; 5 fF; 60 muW; 90 nm; cell capacitance; concordant memory design; embedded DRAM macro; high-accuracy post-fabrication tuning; logic compatible CMOS process; low-noise core architecture; random-cycle operation; reduced data retention power; sensing accuracy; statistical integration; Degradation; Energy consumption; Energy management; Fluctuations; Leakage current; Memory management; Parasitic capacitance; Phased arrays; Signal to noise ratio; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1494071

Filename

1494071

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1673414