Title :
A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology
Author :
Kyung, Kye Hyun ; Kim, Chi Wook ; Lee, Jae Young ; Kook, Jeong Hoon ; Seo, Sung Min ; Kim, Du Yeul ; Kim, Jun Hyung ; Sunwoo, Jung ; Lee, Hi Choon ; Kim, Chul Soo ; Jeong, Byung Hoon ; Sohn, Young Soo ; Hong, Sang Pyo ; Lee, Jae Hyung ; Yoo, Jei Hwan ; Ch
Author_Institution :
Samsung, Hwasung, South Korea
Abstract :
A 1.8V, 800Mbit/s/pin, 2GB DDR2 SDRAM is developed using an 80nm triple metal technology. With the triple metal technology, NMOS precharge I/O scheme and statistical analysis, DDR800 4-4-4 performance is achieved at 1.8V. For mass production, a high-speed clock using an on chip PLL and an address-pin-reduction mode are employed.
Keywords :
DRAM chips; MOS integrated circuits; clocks; phase locked loops; statistical analysis; 1.8 V; 2 GB; 80 nm; 800 Mbit/s; DDR2 SDRAM; DDR800 4-4-4 performance; NMOS precharge I/O scheme; address-pin-reduction mode; high-speed clock; mass production; on chip PLL; statistical analysis; triple metal technology; Circuits; Decoding; Fuses; Packaging; Random access memory; Repeaters; SDRAM; Standards development; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494072
