• DocumentCode
    1673460
  • Title

    A 20GB/s 256MB DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

  • Author

    Kim, Kyu-hyoun ; Sohn, Young-Soo ; Kim, Chan-Kyoung ; Lee, Dong-Jin ; Byun, Gyung-Su ; Lee, Hoon ; Lee, Jae-Hyoung ; Sunwoo, Jung ; Choi, Jung-Hwan ; Chai, Jun-Wan ; Kim, Changhyun ; Cho, Soo-In

  • Author_Institution
    Samsung, Hwasung, South Korea
  • fYear
    2005
  • Firstpage
    470
  • Abstract
    A 20GB/s 1.8V 256MB DRAM is designed and fabricated using an 80nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with a cascaded pre-emphasis transmitter to achieve a 10Gbit/s/pin data rate.
  • Keywords
    CMOS memory circuits; DRAM chips; cascade networks; oscillators; phase locked loops; 1.8 V; 10 Gbit/s; 20 GB/s; 256 MB; 80 nm; CMOS process; DRAM; cascaded pre-emphasis transmitter; inductorless quadrature PLL; inductorless tetrahedral oscillator; inherent quadrant phases; Clocks; Frequency conversion; Inverters; Jitter; Noise reduction; Phase locked loops; Random access memory; Ring oscillators; Transmitters; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494073
  • Filename
    1494073
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1673460