Implementation of high speed radix-10 parallel multiplier using Verilog

The emerging computational complexities arises the need of fast multiplication unit. The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial products can be reduced by using higher radix multiplication. For better speed applications a radix-10 multiplier is proposed which uses recoded multiplier digits as in conventional parallel multiplier design. The multiplier digits are encoded using Signed Digit (SD) radix-10 method which converts the digit set to {-5 to 5} from {0 to 9} and also generate a sign bit. This recoding leads to minimized calculations as only five multiples are required to be calculated and the negative multiples are obtained using 2´s complement approach. The negative multiples are used when sign bit is high. A different approach is availed in the multiples generation of the multiplicand digit and during accumulation of partial product obtained during multiplication procedure. A modified BCD adder is used which eliminates the post correction while calculating the sum of two BCD digits. The modified architecture eliminates the extra recoding logic thereby reducing the area of overall architecture. This paper delivers the design and implementation of 16-Bit multiplication unit. The design entry is done in Verilog Hardware Description Language (HDL) and simulated using ISIM Simulator. It is synthesized and implemented using Xilinx ISE 12.2. Synthesis results have shown that 20.3% reduction in 4-Input LUTs and 20.4% reduction in the number of slices is observed in the modified methodology. Further 11.5% reduction of maximum combinational path delay is also observed in the modified architecture, thereby leading to high speed multiplication for VLSI applications.