Title :
A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications
Author :
Takeda, Koichi ; Hagihara, Yasuhiko ; Aimoto, Yoshiharu ; Nomura, Masahiro ; Nakazawa, Yoetsu ; Ishii, Toshio ; Kobatake, Hiroyuki
Author_Institution :
NEC Corp., Sagamihara, Japan
Abstract :
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-Vdd and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum Vdd of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.
Keywords :
CMOS memory circuits; SRAM chips; high-speed integrated circuits; integrated circuit design; low-power electronics; 0.5 V; 20 ns; 440 mV; 64 kbit; 90 nm; CMOS technology; NMOS transistors; access time; high-speed applications; low-voltage circuits; read-static-noise-margin-free SRAM cell; CMOS logic circuits; Delay; Dynamic voltage scaling; Energy consumption; Inverters; Leakage current; MOSFETs; National electric code; Random access memory; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494077
