Title :
5.7 GHz 0.18 μm CMOS gain-controlled LNA and mixer for 802.11a WLAN applications
Author :
Chu, Yuan-Kai ; Liao, Che-Hong ; Chuang, Huey-Ru
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A 5.7 GHz 0.18 μm CMOS gain-controlled differential LNA and a single-ended CMOS mixer for 802.11a WLAN applications are presented. The differential LNA, fabricated with the 0.18 μm 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The single-ended CMOS mixer uses a single balance topology. Measurements of the CMOS components are performed by using a FR-4 PCB test fixture. The LNA exhibit noise figure of 3.7 dB, linear gain of 12.5 dB, P1dB of -11dBm, and gain tuning range of 6.9 dB. The mixer with a 280 MHz IF has a conversion gain -4.5 dB, input P1dB 0 dBm, and noise figure 14.6 dB. LO-RF isolation is 20 dB and LO-IF isolation is 24 dB. The power consumption of the differential LNA is 14.4 mW and that of the mixer is 10.4 mW from a 1.8 V power supply.
Keywords :
CMOS analogue integrated circuits; MMIC amplifiers; MMIC mixers; differential amplifiers; field effect MMIC; integrated circuit noise; wireless LAN; -4.5 dB; 0.18 micron; 1.8 V; 10.4 mW; 12.5 dB; 14.4 mW; 14.6 dB; 1P6M standard CMOS process; 280 MHz; 3.7 dB; 5.7 GHz; 802.11a WLAN applications; CMOS LNA; FR-4 PCB test fixture; current-reuse technology; gain tuning range; gain-controlled differential LNA; linear gain; noise figure; power consumption; single balance topology; single-ended CMOS mixer; CMOS process; CMOS technology; Energy consumption; Fixtures; Gain; Noise figure; Performance evaluation; Testing; Topology; Wireless LAN;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
Print_ISBN :
0-7803-7694-3
DOI :
10.1109/RFIC.2003.1213930