Title :
PVT-aware leakage reduction for on-die caches with improved read stability
Author :
Kim, Chris H. ; Jae-Joon Kim ; Chang, Ik-Joon ; Roy, Kaushik
Author_Institution :
Minnesota Univ., Minneapolis, MN, USA
Abstract :
A run-time leakage reduction technique for SRAM caches considers architecture and behavior to achieve an optimal tradeoff between overhead energy and leakage savings. A 16kB SRAM shows a 94.2% cell leakage reduction with a 2% performance penalty. Fabricated in a 0.18 μm 6M CMOS process, the 3.2mm×2.9mm die also shows 25% improvement in read stability.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; leakage currents; 0.18 micron; 16 kB; CMOS process; PVT-aware leakage reduction; SRAM caches; on-die caches; overhead energy; read stability; CMOS technology; Circuit stability; Gate leakage; Random access memory; Runtime; Signal design; Signal generators; Stress; Switching circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494079
