• DocumentCode
    1673662
  • Title

    The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium®-family processor

  • Author

    Wuu, John ; Weiss, Don ; Morganti, Charles ; Dreesen, Michael

  • Author_Institution
    Intel, Fort Collins, CO, USA
  • fYear
    2005
  • Firstpage
    488
  • Abstract
    The 24MB level-3 cache on a dual-core Itanium® processor has more than 1.47G transistors. The cache uses an asynchronous design to reduce latency and power, and it includes other power saving and reliability improvement features. The 5-cycle array operates above 2GHz at 0.8V and 85°C while consuming less than 4.2W.
  • Keywords
    asynchronous circuits; cache storage; delays; microprocessor chips; power consumption; 0.8 V; 24 MB; 5-cycle array; 85 degC; asynchronous level-3 cache; dual-core Itanium-family processor; on-chip level-3 cache; power saving; reduced latency; reliability improvement; Circuits; Clocks; Decoding; Delay; Latches; Microprocessors; Process planning; Random access memory; Repeaters; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494082
  • Filename
    1494082
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1673662