An integrable trench LDMOS transistor on SOI for RF power amplifiers in PICs

In this paper, improvement in the RF performance of a conventional LDMOS transistor on silicon-on-insulator (SOI) is investigated by incorporating trenches in the drift region and we propose a lateral trench RF LDMOS device. The proposed structure consists of three trenches built in the n-drift region. A single vertical gate is placed centrally in the trench between p-body region thus forming dual channel for parallel current conduction. The other two identical trenches located symmetrically on sides of p-body are filled with oxide thereby enhancing reduced-surface-field (RESURF) effect. The performance of the proposed device is analysed and compared with that of the conventional LDMOS using 2D numerical simulations. With 62% increase in breakdown voltage (BV) the proposed LDMOS exhibits nearly 2 times higher output current (I_D), 23% lower threshold voltage (V_th) and 67% improvement in peak transconductance (g_m) when compared to the conventional LDMOS for identical drift region doping and cell pitch. Furthermore, the trench structure provides 47% and 11% improvement in cutoff frequency (f_T) and maximum oscillation frequency (f_max), respectively over the conventional counterpart. The device is very promising as an integrable transistor for RF power amplifiers in PICs.