Title :
An efficient approach for estimating the impact of SSO noise on LPDDR2 timing budget
Author :
Mishra, Yagya D. ; Hashmi, Mohammad S. ; Mishra, Akhilesh C.
Author_Institution :
Dept. of Electron. & Comm. Eng., IIIT Delhi, New Delhi, India
Abstract :
In this paper, a new methodology for analysis of SSO effect on jitter value based on IBIS v5.0 is proposed. Subsequently, investigation of the impact of simultaneous switching output (SSO) noise, jitter and timing closure of a complete 8 bit LPDDR2 bus at 400 MHz obtained using this developed methodology is presented. Experimental results obtained on automotive microcontrollers using the developed methodology and conventional spice based techniques compare favourably in terms of accuracy. In addition, the developed technique is also manifold faster when compared to spice based technique and this essentially demonstrate the effectiveness of the proposed approach.
Keywords :
automotive electronics; integrated circuit noise; jitter; logic design; microcontrollers; synchronisation; IBIS v5.0; LPDDR2 timing budget; SPICE based techniques; SSO noise; automotive microcontrollers; frequency 400 MHz; jitter value; simultaneous switching output noise; timing closure; Clocks; Jitter; Noise; Rails; SPICE; Switches; Timing; IBIS; SSO; jitter; power integrity; signal integrity;
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
DOI :
10.1109/ISVDAT.2015.7208085
