DocumentCode
1673924
Title
A sub-10ps multi-phase sampling system using redundancy
Author
Lee, Li-Min ; Yang, Chih-Kong Ken
Author_Institution
California Univ., Los Angeles, CA, USA
fYear
2005
Firstpage
510
Abstract
The feasibility of sampling with clock phases spaced by a bin size of <10ps for a multi-channel system in a 0.18 μm CMOS technology is demonstrated. The phase spacing is limited only by uncorrelated thermal noise in the system. Redundancy is introduced in addition to interpolators and offset compensation to reduce static errors to 1.5ps.
Keywords
CMOS integrated circuits; VLSI; integrated circuit testing; redundancy; signal sampling; thermal noise; watches; 0.18 mm; CMOS technology; clock phases; interpolators; multi-phase sampling system; offset compensation; reduced static errors; redundancy; uncorrelated thermal noise; Circuits; Clocks; Jitter; Noise reduction; Phase measurement; Phase noise; Redundancy; Sampling methods; System testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1494093
Filename
1494093
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