An Efficient Implementation of the Gradient-Based Hough Transform Using DSP Slices and Block RAMs on the FPGA

The gradient-based Hough transform is an improvement of the original Hough transform. It is utilized to reduce substantially the computation quantity and make the detection more accurate using gradient information. The main contribution of this paper is to present an efficient implementation of the gradient-based Hough transform for straight lines detection using a Xilinx Virtex-7 FPGA with embedded DSP slices and block RAMs. We implemented the circuit using 13 DSP48E1 slices, 180 block RAMs with 36Kbits and 8 block RAMs with 18Kbits. The experimental results show that the architecture runs in 260.061MHz and for an n×n grayscale image, our circuit can perform in n² + (√2 + 2)n + 232 clock cycles including the computation of gradient information.