Title :
A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery
Author :
Chung, Daehyun ; Ryu, Chunghyun ; Kim, Hyungsoo ; Lee, ChoonHeung ; Kim, Jaedong ; Kim, JinYoung ; Bae, KiCheol ; Yu, Jiheon ; Lee, SeungJae ; Yoo, Hoijun ; Kim, Joungho
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
A chip-package hybrid DLL and clock distribution network provides low-jitter clock signals by utilizing separate supply connections and lossless package layer interconnections instead of on-chip global wires. The hybrid scheme has 78psco jitter and under 240mV digital noise at 500MHz, while a conventional scheme has a 172psp-p jitter under the same conditions.
Keywords :
CMOS integrated circuits; clocks; delay lock loops; timing jitter; CMOS; chip-package DLL loop; clock distribution network; digital noise; hybrid DLL loop; lossless package layer interconnections; low-jitter clock delivery; CMOS technology; Circuit noise; Clocks; Delay; Integrated circuit interconnections; Jitter; Noise generators; Packaging; Repeaters; Silicon;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494095
