Title :
CMOS technology evolution: from 1 μm to 0.1 μm
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
This paper reviews a number of key device and technology advances that enabled CMOS VLSI technology to evolve from 1 μm to 0.1 μm. They include: lithography, DRAM cell structure, shallow trench isolation, power supply voltage, thin gate oxide, n+/p+ polysilicon gate, shallow source-drain junctions, channel doping profile, and multi-level interconnect. Challenges to future scaling of CMOS technology are addressed at the end
Keywords :
CMOS integrated circuits; DRAM chips; doping profiles; integrated circuit interconnections; isolation technology; lithography; semiconductor doping; 0.1 to 1 micron; CMOS technology evolution; DRAM cell structure; VLSI technology; channel doping profile; lithography; multi-level interconnect; n+/p+ polysilicon gate; power supply voltage; shallow source-drain junctions; shallow trench isolation; thin gate oxide; Apertures; CMOS logic circuits; CMOS technology; Capacitors; Isolation technology; Lenses; Lithography; Logic devices; Random access memory; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.500151
