A fast settling, low phase noise, digitally controlled 2.4 GHz CMOS 12-bit ΣΔ fractional-N synthesizer with programmable step sizes

Frequency synthesizer has been a key element in various communication systems covering a wide range of applications. The requirements on step sizes, channel selection, offset in output frequency and frequency resolution vary with application, data transmission speed and data modulation scheme etc. The recent evolutions have encouraged development of integrated fractional-N synthesizer that features application versatility. A 2.4 GHz CMOS 12-bit ΣΔ fractional-N synthesizer using 0.35 μm CSM process is designed. Unlike to the conventional architectures, it is based on two input data words and features programmable step sizes (18.4 kHz to 0.5 MHz), programmable channels (64), programmable output frequency offsets (0 to 37 MHz), 19 mA current consumption @ 3V Supply, phase noise of -110 dBc/Hz @1 MHz, settling time <37 μS, %32/33 DMP and 4.2 mm² die area.