A 1.8 V monolithic CMOS nested-loop frequency synthesizer for GSM receivers at 1.8 GHz

Author

Murji, Riman ; Deen, M. Jamal

Author_Institution

Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada

fYear

2003

Firstpage

291

Lastpage

294

Abstract

A low-power, integrated 1.8 GHz nested-loop frequency synthesizer for GSM at 1.8 GHz in a 0.18 μm CMOS technology is presented. The synthesizer consists of two voltage-control oscillators (VCOs) and uses band switching MIM capacitors and analog tuning circuits using pMOS capacitors. Both VCOs and loop-filters are integrated on-chip. The IF VCO phase noise is -131 dBc/Hz@600 kHz from a 450 MHz carrier and the RF VCO phase noise is -121 dBc/Hz@600 kHz from a 1.8 GHz carrier. The power consumption of this nested-loop frequency synthesizer is 36 mW@1.8 V and has a die size of 3000 μm × 2000 μm.

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF oscillators; cellular radio; circuit tuning; frequency synthesizers; low-power electronics; phase locked loops; phase noise; radio receivers; voltage-controlled oscillators; 0.18 micron; 1.8 GHz; 1.8 V; 36 mW; CMOS nested-loop frequency synthesizer; GSM receiver; IF VCO; RF VCO; analog tuning circuit; band switching MIM capacitor; loop filter; low-power operation; monolithic integration; pMOS capacitor; phase noise; voltage controlled oscillator; CMOS technology; Circuit optimization; Frequency synthesizers; GSM; Integrated circuit technology; MIM capacitors; Phase noise; Switched capacitor circuits; Switching circuits; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-7694-3

Type

conf

DOI

10.1109/RFIC.2003.1213946

Filename

1213946