Title :
A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients
Author :
Bae, Seung-Jun ; Chi, Hyung-Joon ; Kim, Hyung-Rae ; Park, Hong-June
Author_Institution :
Pohang Univ. of Sci. & Technol., South Korea
Abstract :
A 3Gbit/s/pin 8b parallel 4-drop single-ended DRAM transceiver is implemented in a 0.25 μm CMOS process. Digital calibrations are performed for equalization and compensation of data skew and offset voltage. A continuously active on-die termination is used to reduce reflections. A phase detector is proposed for the digital DLL to achieve the S/H time of 10ps.
Keywords :
CMOS integrated circuits; DRAM chips; adaptive equalisers; calibration; clocks; delay lock loops; phase detectors; sample and hold circuits; transceivers; 0.25 mm; 10 ps; 3 Gbit/s; 4-drop DRAM interface; 8 bit; CMOS process; S/H time; continuously active on-die termination; digital DLL; digital calibration; equalization skew; offset coefficients; phase detector; reduced reflections; single-ended transceiver; Calibration; Circuits; Clocks; Equalizers; Multiplexing; Random access memory; Reflection; Resistors; Transceivers; Transmitters;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494098
