Title :
Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply
Author :
Ker, Ming-Dou ; Chen, Shih-Lun
Author_Institution :
Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Abstract :
This work presents a mixed-voltage I/O buffer realized with 1×VDD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13 μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×VCD, and even 6×VDD input signals.
Keywords :
CMOS integrated circuits; buffer circuits; low-power electronics; 0.13 micron; 1 V; CMOS process; dynamic gate-bias circuit; gate-oxide reliability; input tolerance; mixed-voltage I/O buffer; CMOS technology; Circuits; Dynamic voltage scaling; Inverters; Logic devices; Power supplies; Protection; Signal generators; Threshold voltage; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494100
