A novel VLSI design of DCTQ processor for FPGA implementation

Author

Jain, Yogesh M. ; Jadhav, Aviraj R. ; Dixit, Harish V. ; Hindole, Akshay S. ; Vadakoott, Jithin R. ; Bilaye, Devendra S.

Author_Institution

Dept. of Electr. Eng., VJTI, Mumbai, India

fYear

2015

Firstpage

1

Lastpage

5

Abstract

In this era of Internet of Things, wherein every `thing´ is integrated within the existing internet architecture, it becomes quite necessary that embedded computing systems process quickly, occupy less area and consume low power. This would enable them to work quickly with real time data and have a large shelf life. As such there is a need for development of optimized algorithms and their efficient implementation in hardware. This paper presents a novel architecture for obtaining DCTQ coefficients suitable for FPGA Implementation. The design is highly parallel and pipelined so as to exploit the massive parallelism of FPGAs and occupies considerably less area (4,244/9,312) with a very high processing speed (148.192 MHz).

Keywords

Internet of Things; VLSI; circuit optimisation; discrete cosine transforms; field programmable gate arrays; logic design; low-power electronics; microprocessor chips; frequency 148.192 MHz; Adders; Clocks; Computer architecture; Discrete cosine transforms; Field programmable gate arrays; Image coding; Random access memory; DCTQ; Efficient; FPGA; Low Power;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Test (VDAT), 2015 19th International Symposium on

Conference_Location

Ahmedabad

Print_ISBN

978-1-4799-1742-6

Type

conf

DOI

10.1109/ISVDAT.2015.7208102

Filename

7208102