DocumentCode :
1674258
Title :
Fault masking in Quantum-dot cellular automata using prohibitive logic circuit
Author :
Nath, Rajdeep Kumar ; Sen, Bibhash ; Daga, Rachit ; Chakraborty, Nilesh ; Tibrewal, Harsh ; Sikdar, Biplab K.
Author_Institution :
CSE Dept., Nat. Inst. of Technol., Durgapur, India
fYear :
2015
Firstpage :
1
Lastpage :
5
Abstract :
This work targets the challenges to design with uncertainty in QCA architecture via characterization of fabrication faults caused due to particular cell displacement in the QCA logic circuit. One of the worst kind of fault to remove is input generated transient fault, called single event upset (SEU). To show the unpredictability of QCA circuits under such faults, the correct input vectors are filtered beyond which the circuit behaves abnormally. The consequence of errors on the circuit is then analysed and test vector(s) is/are obtained to identify such faults. A prohibitive logic circuit is designed which allows just the right inputs and/or equivalent inputs to the faulty inputs. SEU transient fault can be avoided by the proposed prohibitive logic circuit to make an initiative towards the green computing.
Keywords :
logic circuits; logic design; logic testing; quantum dots; radiation hardening (electronics); vectors; QCA architecture; QCA logic circuit; SEU transient fault; cell displacement; fabrication faults; fault masking; green computing; prohibitive logic circuit; quantum-dot cellular automata; single event upset; test vector; Circuit faults; Computer architecture; Logic gates; Microprocessors; Single event upsets; Synchronization; Transient analysis; Fault masking; Prohibitive logic; Quantum-dot cellular automata (QCA); Single event upset (SEU); Transient fault;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
Type :
conf
DOI :
10.1109/ISVDAT.2015.7208103
Filename :
7208103
Link To Document :
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