DocumentCode :
1674379
Title :
A loop routing approach for decreasing critical path delay
Author :
Qiao, Changge ; Hong, Xianlong
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear :
1995
Firstpage :
355
Lastpage :
357
Abstract :
In this paper, we propose a loop routing performance optimization approach, which create loops in the existing routing trees for the purpose of decreasing delay of the selected critical path or maximum delay for a net. The interconnect tree is formulated as a tree of distributed transmission lines and Elmore delay is used for delay calculation. It is proven that the delay of a selected critical path or maximum delay for a net can be reduced dramatically by introducing a new link with appropriate R, C values between the reference node and the critical node in the existing tree topology. We give the wire length selection on the basis of pre-calculated time delay of node and the resistance and capacitance array. Experiments show the effectiveness of our approach for critical path delay minimization
Keywords :
circuit optimisation; delays; distributed parameter networks; minimisation; network routing; trees (mathematics); Elmore delay; capacitance array; critical path delay minimization; distributed transmission lines; interconnect tree topology; loop routing; maximum delay; network optimization; resistance array; wire length; Capacitance; Computer science; Delay effects; Delay estimation; Delay lines; Optimization; Routing; Topology; Transmission lines; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
Type :
conf
DOI :
10.1109/ICSICT.1995.500164
Filename :
500164
Link To Document :
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