An extractor for 3-D parasitic capacitance and resistance

In the development of integrated circuits, parasitic parameters associated with interconnections affect the circuit speeds and functionality greatly in the case of sub-micron process. Many works have been done on the efficient calculation of these parameters. In this paper, a three-dimensional parasitic capacitance extractor is presented. The Boundary Element Method (BEM) is employed to deal with the Laplace´s equation. The simulations and the comparisons showed that the experimental results are excellent agreement with the measured ones, and our extractor is effective in simulation of 3-D parasitic capacitances