DocumentCode :
1674592
Title :
Net weighing based timing driven standard cell placer
Author :
Pawanekar, Sameer ; Trivedi, Gaurav
Author_Institution :
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
fYear :
2015
Firstpage :
1
Lastpage :
6
Abstract :
In this paper, a timing driven placement engine which is based on the partition driven method is described. In the proposed method, the netlist are partitioned recursively to form smaller sub-circuits and to perform simulated annealing at a later stage when sub-circuits are relatively small. The proposed timing optimization approach is based on net weighting. We present three different approaches for performing net weighting based placement during partitioning based flow of the proposed placer. The three approaches namely PartWeight, CritWeight and SAweight presented in this paper give an average performance improvement of 106%, 18% and 27% over Cadence Encounter´s Amoeba. Half Perimeter obtained by the proposed placer for the benchmark designs are comparable to the industry standard tool Amoeba.
Keywords :
integrated circuit layout; simulated annealing; Amoeba; Cadence Encounter; CritWeight; PartWeight; SAweight; benchmark designs; net weighing; netlist; partition driven method; simulated annealing; timing driven placement engine; Benchmark testing; Delays; Partitioning algorithms; Simulated annealing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
Type :
conf
DOI :
10.1109/ISVDAT.2015.7208114
Filename :
7208114
Link To Document :
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