• DocumentCode
    1674628
  • Title

    A dual-band tri-mode CDMA IF receiver with programmable channel-match filter

  • Author

    Cho, Joshua ; Good, Pete ; Kamat, Manish ; McCarthy, Evan ; Rampmeier, Keith ; Cops, Wim ; El Moznine, Ahdellatif ; Truong, Hiep ; He, Yong ; Yates, Dave ; Taskov, Georgi ; Lee, Chang-Hyeon ; Koh, Dongsoo ; Lloyd, Stephen

  • Author_Institution
    Skyworks Solutions Inc., Irvine, CA, USA
  • fYear
    2003
  • Firstpage
    391
  • Lastpage
    394
  • Abstract
    An integrated dual-band tri-mode CDMA IF receiver with programmable channel-match filter is presented. The cascaded VGA and filter chain provides maximum voltage gain of 93 dB with noise figure of <7.5 dB. It also provides >88 dB of gain control range. The IF VCO, which operates at 2×LO for PCS mode and 4×LO for AMPS/CDMA mode, achieves -131 dBc/Hz of phase noise at 900 kHz offset with an external tank. An area-efficient combined channel-match filter chain for both CDMA/PCS and AMPS mode is realized by changing the clock frequency of a switched-capacitor filter and by switching-in and -out capacitors for the continuous time and switch-cap filters depending on the mode of operation. The filter chain meets all the blocker requirements for both CDMA/PCS and AMPS modes. Combining the CDMA/PCS and AMPS filter saves 30% die area compared to separate filter chains. The IC is fabricated in Jazz´s 35 GHz ft silicon BiCMOS process and packaged into a 48-pin 6 mm×6 mm land grid array (RF-LGA™) chipscale package.
  • Keywords
    BiCMOS integrated circuits; chip scale packaging; code division multiple access; continuous time filters; integrated circuit design; integrated circuit measurement; integrated circuit noise; phase noise; radio receivers; radiofrequency amplifiers; switched capacitor filters; voltage-controlled oscillators; 35 GHz; 6 mm; 7.5 dB; 93 dB; AMPS/CDMA mode; IF VCO; PCS mode; Si; cascaded VGA; continuous time filters; die area reduction; dual-band tri-mode CDMA IF receivers; external tank circuits; filter chain blocker requirements; gain control range; land grid array chipscale packaging; maximum voltage gain; noise figures; phase noise; programmable channel-match filter chains; silicon BiCMOS process; switched-capacitor filter clock frequency; variable gain amplifiers; BiCMOS integrated circuits; Dual band; Filters; Gain control; Integrated circuit packaging; Multiaccess communication; Noise figure; Personal communication networks; Voltage; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
  • ISSN
    1529-2517
  • Print_ISBN
    0-7803-7694-3
  • Type

    conf

  • DOI
    10.1109/RFIC.2003.1213969
  • Filename
    1213969