Title :
Detection and analysis of hardware trojan using scan chain method
Author :
Rithesh, M. ; Bhargav, Ram B. V. ; Harish, G. ; Yellampalli, Siva
Author_Institution :
VLSI Dept., VTU Extension Centre UTL Technol. Ltd., Bangalore, India
Abstract :
Due to the globalization of the Integrated Circuit manufacturing industry and wide use of third party IP in the modern SoCs has opened the backdoor for Hardware Trojan insertion. The detection of Hardware Trojan is challenging because of its very rare activation mechanism and unpredictable change in the functionality of the system. This paper proposes a new hardware Trojan detection scheme using power analysis and experiments the insertion and detection of hardware Trojan using existing scan chain efficiently in ISCAS´89 benchmark circuits.
Keywords :
benchmark testing; integrated circuit manufacture; invasive software; system-on-chip; IP; ISCAS´89 benchmark circuits; SoC; hardware trojan insertion; integrated circuit manufacturing industry; power analysis; scan chain; Benchmark testing; Clocks; Fabrication; Hardware; Logic gates; Radiation detectors; Trojan horses; Application Specific Integrated Circuit (ASIC); Dummy Scan F l i p Flop (DSFF); Graphical Data System II (GDSII); Integrated Circuit (IC); Register Transfer Level (RTL) SoC; Ring Oscillator Network (RON);
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
DOI :
10.1109/ISVDAT.2015.7208124
