Title :
A CMOS dual-band tri-mode chipset for IEEE 802.11a/b/g wireless LAN
Author :
Mehta, S. ; Zargari, M. ; Jen, S. ; Kaczynski, B. ; Lee, M. ; Mack, M. ; Mendis, S. ; Onodera, K. ; Samavati, H. ; Si, W. ; Singh, K. ; Terrovitis, M. ; Weber, D. ; Su, D.
Author_Institution :
Atheros Commun., Sunnyvale, CA, USA
Abstract :
This paper presents the design of a dual-band, tri-mode wireless LAN chipset for IEEE 802.11a/b/g. The chipset, designed in 0.25/spl mu/m standard CMOS, features a 5GHz RF transceiver, a 2.4GHz RF transceiver, and a baseband processor with media access controller. The overall design achieves a measured sensitivity of at least -70dBm at 54Mbps and -92dBm at 6Mbps for IEEE 802.11a/g as well as -94dBm at 1Mbps for 802.11b.
Keywords :
CMOS integrated circuits; radiofrequency integrated circuits; transceivers; wireless LAN; 0.25 micron; 1 Mbit/s; 2.4 GHz; 5 GHz; 54 Mbit/s; 6 Mbit/s; CMOS dual-band tri-mode chipset; IEEE 802.11a/b/g wireless LAN; RF transceiver; baseband processor; media access controller; Baseband; CMOS process; Dual band; Filters; Physical layer; RF signals; Radio frequency; Switches; Transceivers; Wireless LAN;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
Conference_Location :
Philadelphia, PA, USA
Print_ISBN :
0-7803-7694-3
DOI :
10.1109/RFIC.2003.1213977
