Instruction cache design space exploration for embedded software applications

Embedded processors with cache memories are used to improve the overall performance of the system. To maintain a trade-off between cache size costs vs. performance, it is required to avoid oversize cache. A quick estimation of cache size at the early stage of design cycle may help the system architect to plan the available chip area among processing core, cache memory, register file and other system components. There are two general approaches to explore the design space. One is the exhaustive simulation and the other is analytical modeling. In general, at a given abstraction level, the former is very time consuming whereas the latter often lacks the accuracy. This paper discusses a hybrid approach, combining analysis and simulation for determining the “best” cache size, beyond which performance penalties are very high, for embedded applications. A rapid technique, based on static analysis followed by simulation of the restricted design space of L1 instruction cache size for embedded application has been proposed in this paper. The technique helps in confining the search space from 20% to 30% of the total search space for different applications of MiBench benchmark suite.