DocumentCode
1674953
Title
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits
Author
Shah, Toral ; Matrosova, Anzhela ; Singh, Virendra
Author_Institution
IIT Bombay, Mumbai, India
fYear
2015
Firstpage
1
Lastpage
2
Abstract
For high end design, delay test becomes increasingly important. The paper proposes a technique to synthesize fully delay testable circuit without any additional control input. Our proposal is based on covering each ROBDD node by Invert-And-Or elements. We have shown that the generated circuit is fully testable either by robust tests or by validatable non-robust tests.
Keywords
combinational circuits; logic testing; Invert-AND-OR circuits; PDF testability; ROBDD nodes; combinational circuit; delay test; Boolean functions; Circuit faults; Combinational circuits; Data structures; Delays; Logic gates; Robustness; Binary Decision Diagram (BDD); Design for testability; Path delay fault (PDF); Robust testable PDF;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location
Ahmedabad
Print_ISBN
978-1-4799-1742-6
Type
conf
DOI
10.1109/ISVDAT.2015.7208130
Filename
7208130
Link To Document