A low-power subthreshold LNA for mobile applications

A fully integrated low power LNA is implemented using 65-nm RF CMOS technology for 2.14-GHz band. By taking the advantage of higher transition frequency of recent technologies, transistors are biased in the moderate inversion region and this permitted scaling down the supply voltage to 0.7 V. Further, the exploration of design spaces from strong to weak inversion led to the development of a low power LNA which consumes a DC power of only 315 μW. For LNA design, PCSNIM (Power Constrained Simultaneous Noise and Input Matching) technique is used to improve noise figure at a given power. With this, a good power match is also achieved at the input where the simulated S11 parameter shows an excellent value of -22 dB. Compared to other existing subthreshold cascode LNAs reported in the literature, it shows reasonably better performance in terms of noise level and power consumption with a noise figure of 3.74 dB and a moderate power gain of 8.7 dB at a core device current consumption of 450 μA.