Title :
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology
Author :
Savani, Vijay ; Devashrayee, N.M.
Author_Institution :
EC Dept., Nirma Univ., Ahmedabad, India
Abstract :
This paper presents characterization of low operating voltage, high speed and power efficient comparator used as a basic building block in speed optimized Analog to Digital Converters (ADC), such as flash ADC. Overall performance of any ADC in terms of speed, resolution and power consumption highly depends on the underlying comparator being used. In this paper, better structure of comparator is implemented and analyzed, which is a combination of modified SR latch and sense amplifier. The comparator is built up by preamplifier and positive feedback latch (back-to-back connected inverter) to enhance the speed. The output of latch is given to the modified SR latch, which provides stable output signal compare to that of conventional dynamic latch structure. The implementation is carried out in 90nm technology in Mentor Graphics´ IC Studio tool and simulation is done in Eldo tool.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); analog to digital converters; dual tail current based dynamic latch comparator; flash ADC; modified SR latch; size 90 nm; CMOS integrated circuits; Clocks; Delays; Latches; Low voltage; Topology; Transistors; ADC; CMOS; Dynamic Latch Comparator Dual tail comparator; SR flip flop;
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
DOI :
10.1109/ISVDAT.2015.7208136
