DocumentCode
1675068
Title
A high speed dual modulus divider in SOI CMOS with stacked current steering phase selection architecture
Author
Mistry, K. ; Redman-White, W. ; Benson, J. ; D´Halleweyn, N.
Author_Institution
Microelectron., Southampton Univ., UK
fYear
2003
Firstpage
471
Lastpage
474
Abstract
This work describes a high frequency dual modulus divider designed and fabricated in a 0.35 μm PDSOI process, employing a stacked topology phase switching scheme. SOI CMOS technology is exploited to allow current re-use in a higher supply voltage than dictated by single device breakdown. Measurements show the circuit operating at 3GHz (Vdd = 6.8V.).
Keywords
CMOS integrated circuits; dividing circuits; high-speed integrated circuits; radiofrequency integrated circuits; silicon-on-insulator; 0.35 micron; 3 GHz; 6.8 V; PDSOI process; RFIC; SOI CMOS technology; current re-use; high-speed dual modulus divider; stacked current steering phase selection architecture; Body regions; Breakdown voltage; CMOS technology; Circuits; Frequency synthesizers; Implants; Isolation technology; Parasitic capacitance; Silicon on insulator technology; Stacking;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
ISSN
1529-2517
Print_ISBN
0-7803-7694-3
Type
conf
DOI
10.1109/RFIC.2003.1213987
Filename
1213987
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