Title :
A 2.4GHz dual-modulus divide-by-127/128 prescaler in 0.35 μm CMOS technology
Author :
Rana, Ram Singh ; Jian, Zhang Chen
Author_Institution :
Inst. of Microelectron., Singapore, Singapore
Abstract :
High speed design solution for high divide-by-value dual modulus prescaler remains a challenge in designing high frequency synthesizers in CMOS technology. This paper presents a dual-modulus divide-by-127/128 prescaler implemented in 0.35 μm CMOS technology operating at 2.4GHz frequency. Unlike the conventional topologies, this design is based on a novel way of dual-modulus division using four transmission gates in critical path. It consumes 4.8mW power from a 3V supply. Measurement results are provided.
Keywords :
CMOS integrated circuits; UHF integrated circuits; dividing circuits; frequency synthesizers; high-speed integrated circuits; low-power electronics; prescalers; 0.35 micron; 2.4 GHz; 3 V; 4.8 mW; CMOS technology; frequency synthesizer; high divide-by-value dual modulus prescaler; high-speed low-power design; CMOS technology; Circuit topology; Combinational circuits; Counting circuits; Delay; Flip-flops; Frequency conversion; Frequency synthesizers; Logic gates; Phase locked loops;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
Print_ISBN :
0-7803-7694-3
DOI :
10.1109/RFIC.2003.1213988
