DocumentCode :
1675208
Title :
Implementation of a high speed multiplier for high-performance and low power applications
Author :
Kumar, G. Ganesh ; Sahoo, Subhendu K.
Author_Institution :
Dept. of Electr. & Electron. Eng., BITS-Pilani, Hyderabad, India
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
The performance of multiplication in terms of speed and power is crucial for most of the Digital Signal Processing (DSP) applications. Many researchers have come up with various multipliers such as array, Booth, carry save, Wallace tree and modified Booth multipliers. However, for the present day applications Vedic multipliers based on Vedic Mathematics are presently under focus due to their high speed and low power consumption. In this paper, we propose a design of 8 and 16-bit multipliers using fast adders (carry save adder, Brent-Kung adder and carry-select adder) to minimize the power-delay product of multipliers intended for high-performance and low-power applications. Implementation results demonstrate that the proposed Vedic multipliers with fast adders really achieve significant improvement in delay, and power-delay product when compared with the conventional multipliers.
Keywords :
adders; digital arithmetic; low-power electronics; multiplying circuits; Brent-Kung adder; Vedic Mathematics; Vedic multiplier; Wallace tree; carry save adder; carry select adder; digital signal processing; fast adder; high speed multiplier; low power electronics; modified Booth multiplier; power delay product; Adders; Arrays; Delays; Digital signal processing; Signal processing algorithms; Very large scale integration; Vedic multiplier; carry save array; carry-select adder; power-delay product;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
Type :
conf
DOI :
10.1109/ISVDAT.2015.7208143
Filename :
7208143
Link To Document :
بازگشت