A methodology to reuse random IP stimuli in an SoC functional verification environment

Hardware IP design verification is performed using exhaustive random stimuli, while incorporating a coverage driven flow. On the other hand, system-on-chip (SoC) verification methodologies, sometimes, use a directed C-based verification approach to validate the functionality of the design. There is no significant randomization exercised in this process. Reuse of IP testbench components for SoC verification has been a desirable methodology, yet has remained a challenge. This paper addresses the challenge by proposing a flow which enables reuse of random IP stimuli for the SoC verification environment, with no changes to the IP testbench and testcase.