DocumentCode
167587
Title
Performance Modeling for Hardware Thread-Level Speculation
Author
Ying-Chieh Wang ; Che-Rung Lee ; Yeh-Ching Chung ; I-Hsin Chung ; Perrone, Michael
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2014
fDate
19-23 May 2014
Firstpage
1457
Lastpage
1464
Abstract
This paper presents a preliminary performance model for hardware Thread-Level Speculation (TLS) in the IBM Blue Gene/Q computer. The model analyzes the TLS behavior and its overhead. We model the scenario when there are 0, 1 and 2 conflicts. The model shows good performance prediction and is verified with experiments. This study helps to understand potential gains from using special purpose TLS hardware to accelerate the performance of codes that, in a strict sense, require serial processing to avoid memory conflicts.
Keywords
performance evaluation; IBM Blue Gene/Q computer; TLS behavior; TLS hardware; hardware thread-level speculation; memory conflicts; performance prediction; preliminary performance model; serial processing; Analytical models; Computational modeling; Delays; Hardware; Instruction sets; Performance gain; Radiation detectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International
Conference_Location
Phoenix, AZ
Print_ISBN
978-1-4799-4117-9
Type
conf
DOI
10.1109/IPDPSW.2014.163
Filename
6969549
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