DocumentCode :
1675916
Title :
Reducing phase noise by proper sizing of MOSFETs in LC tuned VCOs
Author :
Li, Ye-Ming ; Connelly, J. Alvin
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2003
Firstpage :
627
Lastpage :
630
Abstract :
This work identifies the relationships between the sizes of the oscillator´s core MOSFETs and the phase noise in the 1/f region. Three packaged 1 GHz VCOs with the same LC lank circuit, but different gate lengths were designed and fabricated in a standard digital 0.6 μm CMOS technology. The minimum gate length (Lmin) of the core MOSFETs does not result in the minimum phase noise. Instead, the minimum phase noise occurs when the gate length is Lopo and Lopt = η·Lmin where η is a parameter that depends upon fabrication process and bias current. From measured results, the phase noise can be further decreased by 2 dBc/Hz at 600 kHz offset from 1 GHz center frequency by using the optimal sizes of the core MOSFETs.
Keywords :
CMOS analogue integrated circuits; MOSFET; UHF integrated circuits; UHF oscillators; circuit tuning; equivalent circuits; integrated circuit design; integrated circuit noise; phase noise; voltage-controlled oscillators; 0.6 micron; 1 GHz; CMOS technology; LC tank circuit; LC tuned VCOs; MOSFET sizing; bias current; core MOSFETs; optimum gate length; phase noise; CMOS digital integrated circuits; CMOS technology; Fabrication; Frequency measurement; MOSFETs; Noise measurement; Optimized production technology; Packaging; Phase noise; Time of arrival estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
ISSN :
1529-2517
Print_ISBN :
0-7803-7694-3
Type :
conf
DOI :
10.1109/RFIC.2003.1214025
Filename :
1214025
Link To Document :
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