DocumentCode
1675953
Title
A 110 MHz 84 dB CMOS programmable gain amplifier with RSSI
Author
Wu, Chun-Pang ; Tsao, Hen-Wai
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2003
Firstpage
639
Lastpage
642
Abstract
This paper describes a CMOS programmable gain amplifier that maintains a 3 dB bandwidth greater than 110 MHz and can provide 84 dB gain control range in 1 dB steps. The PGA can also be operated in a low power mode with 3 dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a ±0.7 dB logarithmic accuracy over 80 dB dynamic range. It achieves a sensitivity of -83 dBm. The amplifier consumes 13 mA from a single 3V supply in high power mode. The chip area including pads occupies 1.5×1.5 mm2.
Keywords
CMOS analogue integrated circuits; gain control; low-power electronics; programmable circuits; wideband amplifiers; 110 MHz; 13 mA; 3 V; 71 MHz; CMOS programmable gain amplifier; CMOS successive logarithmic detecting amplifier; RSSI circuit; bandwidth; dynamic range; gain control; low power mode; Bandwidth; Baseband; Circuits; Dynamic range; Electronics packaging; Frequency; Gain control; Maintenance engineering; Power engineering and energy; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
ISSN
1529-2517
Print_ISBN
0-7803-7694-3
Type
conf
DOI
10.1109/RFIC.2003.1214028
Filename
1214028
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