Title :
Reconfigurable Asynchronous Logic
Author_Institution :
Comput. Syst. Lab., Cornell Univ., Ithaca, NY
Abstract :
Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuit-level flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs
Keywords :
asynchronous circuits; logic design; reconfigurable architectures; FPGA; asynchronous logic mapping; circuit-level flexibility; mapping complexity; reconfigurable asynchronous logic; reconfigurable dataflow architecture; Clocks; Design methodology; Energy consumption; Field programmable gate arrays; Logic circuits; Logic design; Logic functions; Manufacturing; Reconfigurable logic; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320939
