Applications-specific microcoded architectures for efficient fixed-rate FFT

Many Fourier transform applications have to operate at fixed sample rates in the low to medium range, especially in signal processing systems. Hence, in order to arrive at efficient implementations, hardware sharing is required as in microcoded architectures. Very efficient application-specific realizations spanning a wide throughput range are proposed for FFT algorithms. Novel single-cycle address computations are presented to obtain these results. Tradeoffs between the architectural alternatives are provided. The designs have been used as test vehicles for the architectural strategy in an automated synthesis tool box geared toward digital signal processing applications