Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Author

Patel, Rakesh H. ; Bereza, William

Author_Institution

Altera Corp., San Jose, CA

fYear

2006

Firstpage

97

Lastpage

100

Abstract

A 275mW at 6.375Gbps high speed serial interface developed in TSMC´s 90nm triple-gate oxide CMOS process and the customized methodology applied to develop and integrate high-speed mixed-signal IPs into FPGA platforms is presented. The risk reduction approach used ensured reliable product, with timely availability. The transceiver IP supports multiple protocols such as PCIe, XAUI, CEI, SDI, etc. There are as many as 20 Rx/Tx transceiver channels embedded in the FPGA. The transceiver achieves better than 10^-12 BER at 6.375Gbps across the XAUI backplane originally designed for 3.125Gbps

Keywords

CMOS integrated circuits; IP networks; field programmable gate arrays; mixed analogue-digital integrated circuits; transceivers; 275 mW; 3.125 Gbit/s; 6.375 Gbit/s; 90 nm; BER; CMOS SerDes FPGA; TSMC; embedded mixed-signal IP development; high speed serial interface; multiple protocols; risk reduction; transceiver IP; transceiver channels; triple-gate oxide CMOS process; Backplanes; Bandwidth; CMOS process; Clocks; Costs; Field programmable gate arrays; Personal communication networks; Protocols; Testing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320979

Filename

4114917