Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry

Author

Le, Jim ; Hanken, Christopher ; Held, Martin ; Hagedorn, Michael ; Mayaram, Kartikeya ; Fiez, Terri S.

Author_Institution

Sch. of EECS, Oregon State Univ., Corvallis, OR

fYear

2006

Firstpage

105

Lastpage

108

Abstract

A pseudo-random number generator implemented in asynchronous logic generates one-fifth the RMS substrate noise compared to the equivalent design in synchronous logic. An asynchronous 8051 processor generates one-third the RMS substrate noise as the equivalent synchronous design. The SNR of a second order delta-sigma modulator (DSM) is not affected by substrate noise due to an asynchronous processor while it experiences 15 dB degradation when the synchronous 8051 processor is clocked near integer multiples of the DSM sampling frequency

Keywords

asynchronous circuits; clocks; delta-sigma modulation; microprocessor chips; random number generation; asynchronous circuit; asynchronous logic; asynchronous processor; clocked digital circuitry; clockless digital circuitry; delta-sigma modulator; pseudorandom number generator; substrate noise generation; synchronous circuit; Circuit noise; Clocks; Degradation; Delta modulation; Frequency; Logic design; Noise generators; Sampling methods; Signal to noise ratio; Synchronous generators; asynchronous circuit; delta sigma modulator; null conventional logic; substrate noise; synchronous circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.321003

Filename

4114919