Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors

Author

Özalevli, Erhan ; Dinc, Hüseyin ; Lo, Haw-Jing ; Hasler, Paul

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA

fYear

2006

Firstpage

149

Lastpage

152

Abstract

We present an implementation of a 4-bit binary-weighted-resistor DAC to be used in quantizers. It is built by using tunable floating-gate CMOS resistors, which exploit the capacitive coupling and voltage storage capabilities of floating-gate transistors and employ scaled-gate linearization technique to suppress the MOSFET nonlinearities. The resistance of these resistors drifts 1.6 middot 10^-3% over the period of 10 years at 25degC. By using these resistors, 15-bit accurate DAC is implemented in 0.5mum CMOS process

Keywords

CMOS integrated circuits; digital-analogue conversion; linearisation techniques; quantisation (signal); resistors; 0.5 micron; 15 bit; 25 C; 4 bit; CMOS process; MOSFET nonlinearities; binary-weighted resistor DAC; capacitive coupling; floating-gate CMOS resistors; floating-gate transistors; scaled-gate linearization technique; tunable linearization; CMOS process; CMOS technology; Calibration; Laser feedback; Resistors; Signal resolution; Temperature; Tunable circuits and devices; Virtual colonoscopy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320867

Filename

4114929