Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology

Low-power circuits are becoming more attractive due to growing of portable device markets. The 1-bit full adder cell is the key building block for any ASIC design. Designing of such low power full-adder circuits is always a challenging concern for any design research. In this paper, we present a new full-adder cell which is designed with multiple pass transistor logic styles, in which some of them use no power/ground rail approach that helps to reduce power. The proposed full-adder was compared with existing low power full adder cells. All these full-adder cells are designed using Generic Process Design Kit (GPDK) 45 nm technology and they are designed in Cadence virtuoso environment and simulated with Cadence spectre simulator. Pre-layout test bench Simulation results shown that proposed full-adder has the advantage of 60% power savings, 32% Speed Improvements and 72% energy improvements.