Concurrent test generation and design for testability

Results of test generation for sequential benchmark circuits are presented. Tests were generated by a concurrent test generation program, CONTEST, which uses a simulation-based directed-search method. All the circuits except one circuit were automatically initialized by the test generator. Although 99% coverage was obtained for one circuit, the coverage was lower for the others. One possible reason for this low coverage is that some circuits have a significant fraction of redundant faults in their nonscan sequential version. Partial scan with sequential test generation was applied to four circuits. These designs required 18 to 43% of flip-flops to be scanned, and fault coverage over 99% was obtained in each case