ASIC test cost/strategy trade-offs

Author

Wheater, Donald L. ; Nigh, Phil ; Mechler, Jeanne Trinko ; Lacroix, Luke

Author_Institution

Microelectron. Div., IBM Corp., Essex Junction, VT, USA

fYear

34608

Firstpage

93

Lastpage

102

Abstract

Supplying cost effective testing for large application specific integrated circuits (ASICs) is one of the key challenges facing the semiconductor industry. Projections suggest that it will not be cost effective to continue in the current test direction. ASIC suppliers must be able to offer a flexible, cost-effective set of test solutions that will meet a variety of customer requirements. This paper presents some of the trade-offs used in developing optimal test strategies

Keywords

application specific integrated circuits; boundary scan testing; built-in self test; costing; design for testability; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; ASIC test cost; BIST; I_DDQ test; application specific integrated circuits; automated diagnostics; cost effective testing; delay test; design for test; functional testing; optimal test strategies; semiconductor industry; structural testing; test pattern generation; trade-offs; Application specific integrated circuits; Circuit testing; Computer aided manufacturing; Costs; Design for testability; Latches; Microelectronics; Observability; Packaging; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1994. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2103-0

Type

conf

DOI

10.1109/TEST.1994.527940

Filename

527940