Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications

A simple to apply designer friendly model is proposed that predicts input frequency dependent harmonic distortion (HD) in first order weakly nonlinear sampling circuits. HD due to steady-state tracking errors typically increases at 20 dB per decade versus input frequency. Application of the model has been simplified to the equivalent of frequency-independent nonlinearity analysis. Analytic expressions of HD for a MOS switch are derived. The first known method quantify the tradeoff between thermally limited signal to noise ratio (SNR) and linearity in the form of spurious free dynamic range (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4, and HD5 versus input frequency of a sample and hold test chip at 19 MSPS fabricated in a 1P5M 0.25mum CMOS process support the conclusions