DocumentCode
1678190
Title
A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling
Author
Zhang, Liang ; Wilson, John ; Bashirullah, Rizwan ; Luo, Lei ; Xu, Jian ; Franzon, Paul
Author_Institution
Dept. of Electr. 7 Comput. Eng., North Carolina State Univ., Raleigh, NC
fYear
2006
Firstpage
265
Lastpage
268
Abstract
A 16-bit on-chip bus with driver pre-emphasis fabricated in 0.25mum CMOS technology attains an aggregate signaling data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional single-ended voltage-mode static bus. The proposed bus is robust against crosstalk noise and occupies comparable routing area to a reference static bus design
Keywords
CMOS integrated circuits; driver circuits; integrated circuit noise; signalling; system buses; 16 bit; 32 Gbit/s; 5 to 10 mm; CMOS technology; delay latency; driver pre-emphasis signaling; on-chip bus; voltage-mode static bus; Aggregates; Bandwidth; CMOS technology; Delay; Driver circuits; Equalizers; Frequency response; Integrated circuit interconnections; Power dissipation; Repeaters;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location
San Jose, CA
Print_ISBN
1-4244-0075-9
Electronic_ISBN
1-4244-0076-7
Type
conf
DOI
10.1109/CICC.2006.320855
Filename
4114955
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