Title :
A 32-bit SoPC implementation of a P5
Author :
Toal, Ciaran ; Sezer, Sakir
Author_Institution :
Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, Ireland
Abstract :
This paper details a system on a programmable chip (SoPC) implementation of a 2.5 Gbps programmable point-to-point-protocol processor (P5) on an FPGA. 32-bit pipelined PPP receiver and transmitter dedicated packet processor circuits are implemented. The Leon processor core is embedded in the system and provides a programmable platform for PPP control protocols including LCP´s and NCP´s and application specific embedded software. An AMBA bus interface is used to interlink the Leon processor to the hardware packet processing unit and presents a standard interface allowing for easy retargeting to other processor platforms. Complex memory control is implemented to enable the microprocessor to handle the extreme data rate of the P5. The high-level system breakdown is described and synthesis results for Altera FPGA technology are presented.
Keywords :
data communication; digital signal processing chips; field programmable gate arrays; packet switching; protocols; storage management; system-on-chip; 2.5 Gbit/s; 32 bit; 32-bit SoPC implementation; AMBA bus interface; Altera FPGA; Leon processor; P5; complex memory control; control protocols; field programmable gate array; hardware packet processing unit; packet processor circuits; programmable point-to-point-protocol processor; receiver; system on a programmable chip; transmitter; Application software; Circuits; Control systems; Electric breakdown; Embedded software; Field programmable gate arrays; Hardware; Microprocessors; Protocols; Transmitters;
Conference_Titel :
Computers and Communication, 2003. (ISCC 2003). Proceedings. Eighth IEEE International Symposium on
Print_ISBN :
0-7695-1961-X
DOI :
10.1109/ISCC.2003.1214168
