A 32-bit SoPC implementation of a P5

This paper details a system on a programmable chip (SoPC) implementation of a 2.5 Gbps programmable point-to-point-protocol processor (P⁵) on an FPGA. 32-bit pipelined PPP receiver and transmitter dedicated packet processor circuits are implemented. The Leon processor core is embedded in the system and provides a programmable platform for PPP control protocols including LCP´s and NCP´s and application specific embedded software. An AMBA bus interface is used to interlink the Leon processor to the hardware packet processing unit and presents a standard interface allowing for easy retargeting to other processor platforms. Complex memory control is implemented to enable the microprocessor to handle the extreme data rate of the P⁵. The high-level system breakdown is described and synthesis results for Altera FPGA technology are presented.