Title :
Two test generation methods for sequential circuits
Author :
Hayashi, Terumine ; Hatayama, Kazumi ; Ishiyama, Shun ; Takakura, Masahiro
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
Abstract :
A description is given of two test generation methods for sequential logic circuits. One method, called the 9ED method, is based on a path sensitization technique and is effective for asynchronous sequential circuits. The other methods, called the 4SP method, is also based on the path sensitization technique and is effective for sequential circuits with a design-for-testability (DFT) structure. The capabilities of these methods are examined with regard to the benchmark circuits prepared for ISCAS´89. The experimental results verified the effectiveness of the 4SP method for these circuits
Keywords :
fault location; logic testing; sequential circuits; 9ED method; asynchronous sequential circuits; benchmark circuits; design-for-testability; logic circuits; path sensitization technique; sequential circuits; test generation methods; Benchmark testing; Circuit faults; Circuit testing; Design for testability; Hazards; Laboratories; Logic testing; Power generation; Sequential analysis; Sequential circuits;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100750
