A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs

Author

Ciccarelli, Luca ; Loparco, Domenico ; Innocenti, Massimiliano ; Lodi, Andrea ; Mucci, Claudio ; Rolandi, Pierluigi

Author_Institution

STMicroelectronics, Agrate Brianza

fYear

2006

Firstpage

309

Lastpage

312

Abstract

Signal propagation delay and leakage power dissipation of FPGAs mainly depend on the routing architecture. In this paper we propose solutions; adopted in an embedded FPGA developed both in 90nm and 65nm STM technology, which minimize the subthreshold current of the switch and connection blocks. Our approach leads to a reduction of more than one order of magnitude of standby leakage, up to 62% of active leakage of the routing architecture, having a small impact on signal delay, without silicon area increase

Keywords

field programmable gate arrays; integrated circuit interconnections; leakage currents; low-power electronics; nanotechnology; 65 nm; 90 nm; STM technology; active leakage reduction; deep submicron FPGA; embedded FPGA; leakage power dissipation; low-power routing architecture; minimized subthreshold current; signal propagation delay; standby leakage reduction; Circuits; Delay; Field programmable gate arrays; Gate leakage; Hardware; Leakage current; Power dissipation; Routing; Silicon; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320889

Filename

4114966